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freescale semiconductor data sheet: technical data contents ? freescale semiconductor, inc., 2008. all rights reserved. document number: mpc5561 rev. 2.0, 27 may 2008 this document provides electrical specifications, pin assignments, and package diagrams for the mpc5561 microcontroller device. for functional characteristics, refer to the mpc5561 microcontroller reference manual . 1 overview the mpc5561 microcontroller (mcu) is a member of the mpc5500 family of micr ocontrollers built on the power architecture? embe dded technology. this family of parts has many new features coupled with high performance cmos technology to provide substantial reduction of cost per feature and significant performance improvement over the mpc500 family. the host processor core of th is device complies with the power architecture embedded category that is 100% user-mode compatible (including floating point library) with the original power pc? user instruction set architecture (uisa). th e embedded architecture enhancements improve th e performance in embedded applications. the core also has additional instructions, including digital signal proc essing (dsp) instructions, beyond the original power pc instruction set. 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . 5 3.3 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.5 esd characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 vrc and por electrical specifications . . . . . . . . . 9 3.7 power-up/down sequencing . . . . . . . . . . . . . . . . 10 3.8 dc electrical specifications. . . . . . . . . . . . . . . . . . 13 3.9 oscillator and fmpll electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 eqadc electrical characteristics . . . . . . . . . . . . . 22 3.11 h7fa flash me mory electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1 mpc5561 324 pbga pinout . . . . . . . . . . . . . . . . 44 4.2 mpc5561 324-pin package dimensions . . . . . . . 45 5 revision history for the mpc5561 data sheet . . . . . . 47 5.1 information changed between revisions 0.1 and 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.2 information changed between revisions 1.0 and 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 mpc5561 microcontroller data sheet by: microcontroller division
mpc5561 microcontroller data sheet, rev. 2.0 overview freescale semiconductor 2 the mpc5500 family of parts contains many new features coupled with high performance cmos technology to provide significant perf ormance improvement over the mpc565. the host processor core of the mp c5561 also includes an instruction set enhancement allowing variable length encoding (vle). this allows optional encoding of mixed 16- and 32-bit instructions. with this enhancement, it is possible to significa ntly reduce the code size footprint. the mpc5561 has two levels of memory hierarchy. the fastest accesses are to the 32-kilobytes (kb) unified cache. the next level in the hierarchy c ontains the 192-kb on-chip internal sram and one megabyte (mb) internal flash memory . the internal sram and flash me mory hold instructions and data. the external bus interface is designed to support mo st of the standard memories used with the mpc5 xx family. the less complex timer functions of the mpc5561 ar e performed by the enhanc ed modular input/output system (emios). the emios? 24 hardware ch annels are capable of single-action, double-action, pulse-width modulation (pwm), a nd modulus-counter operations. moto r control capabilities include edge-aligned and center-aligned pwm. off-chip communication is performed by a suite of se rial protocols including controller area networks (flexcans), enhanced deserial/seria l peripheral interfaces (d spis), and enhanced serial communications interfaces (escis). the parallel digital interface (pdi ) block provides a glueless in terface from the mpc5500 family of devices to high speed external para llel devices such as analog to digital convertors (adcs) and image sensors. the pdi module, wi th its internal direct memory access (dma) engine, moves external parallel data into system memory with minimum intervention from the host processor. th e host processor can also read data from the pdi vi a an interrupt directly. the mcu has an on-chip 40-channel enhanced que ued dual analog-to-digital converter (eqadc). the system integration unit (siu) performs several chip-wide configuration f unctions. pad configuration and general-purpose input and output (g pio) are controlled from the si u. external interrupts and reset control are also determined by th e siu. the internal multiplexer submodule provides multiplexing of eqadc trigger sources and extern al interrupt signal multiplexing. the flexray controller provides functional node ne tworking, with static a nd dynamic host access, to develop highly dependable automotive control systems that require the fu ll implementation of the flexray protocol, as published in flexray protocol specification 2.0 . the flexray module uses fault-tolerant, time-triggered events and cl ock synchronization mechanis ms to maintain the global time of the functional nodes. bus guardian operations ar e available for each channel in a multi- or redundant-channel configuration.
ordering information mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 3 2 ordering information figure 1. mpc5500 family part number example unless noted in this data sheet, all specifications apply from t l to t h . table 1. orderable part numbers freescale part number 1 1 all devices are ppc5561, rather than mpc5561 or spc 5561, until product qualifications are complete. not all configurations are available in the ppc parts. package description speed (mhz) operating temperature 2 2 the lowest ambient operating temperature is referenced by t l ; the highest ambient operating temperature is referenced by t h . nominal max. 3 (f max ) 3 speed is the nominal maximum frequency. max. speed is t he maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm; and 135 mhz parts allow for 132 mhz system clock + 2% fm. min. (t l )max. (t h ) mpc5561mvz132 mpc5561 324 package lead-free (pbfree) 132 135 ?40 c 125 c mpc5561mvz112 112 114 mpc5561mvz80 80 82 mpc5561mzq132 mpc5561 324 package leaded (snpb) 132 135 ?40 c 125 c mpc5561mzq112 112 114 mpc5561mzq80 80 82 mpc m 80 r qualification status core code device number temperature range package identifier operating frequency (mhz) tape and reel status temperature range m = ?40 c to 125 c package identifier zq = 324pbga snpb vz = 324pbga pb-free operating frequency 80 = 80 mhz 112 = 112 mhz 132 = 132 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre qualification m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow 5561 zq note: not all options are available on all devices. refer to ta b l e 1 .
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 4 3 electrical characteristics this section contains detailed information on power c onsiderations, dc/ac electric al characteristics, and ac timing specifications for the mcu. 3.1 maximum rating table 2. absolute maximum ratings 1 spec characteristic symbol min. max. unit 1 1.5 v core supply voltage 2 v dd ?0.3 1.7 v 2 flash program/erase voltage v pp ?0.3 6.5 v 4 flash read voltage v flash ?0.3 4.6 v 5 sram standby voltage v stby ?0.3 1.7 v 6 clock synthesizer voltage v ddsyn ?0.3 4.6 v 7 3.3 v i/o buffer voltage v dd33 ?0.3 4.6 v 8 voltage regulator control input voltage v rc33 ?0.3 4.6 v 9 analog supply voltage (reference to v ssa )v dda ?0.3 5.5 v 10 i/o supply voltage (fast i/o pads) 3 v dde ?0.3 4.6 v 11 i/o supply voltage (slow and medium i/o pads) 3 v ddeh ?0.3 6.5 v 12 dc input voltage 4 v ddeh powered i/o pads v dde powered i/o pads v in ?1.0 5 ?1.0 5 6.5 6 4.6 7 v 13 analog reference high voltage (reference to v rl )v rh ?0.3 5.5 v 14 v ss to v ssa differential voltage v ss ? v ssa ?0.1 0.1 v 15 v dd to v dda differential voltage v dd ? v dda ?v dda v dd v 16 v ref differential voltage v rh ? v rl ?0.3 5.5 v 17 v rh to v dda differential voltage v rh ? v dda ?5.5 5.5 v 18 v rl to v ssa differential voltage v rl ? v ssa ?0.3 0.3 v 19 v ddeh to v dda differential voltage v ddeh ? v dda ?v dda v ddeh v 20 v ddf to v dd differential voltage v ddf ? v dd ?0.3 0.3 v 21 v rc33 to v ddsyn differential voltage spec has been moved to ta bl e 9 dc electrical specifications , spec 43a. 22 v sssyn to v ss differential voltage v sssyn ? v ss ?0.1 0.1 v 23 v rcvss to v ss differential voltage v rcvss ? v ss ?0.1 0.1 v 24 maximum dc digital input current 8 (per pin, applies to all digital pins) 4 i maxd ?2 2 ma 25 maximum dc analog input current 9 (per pin, applies to all analog pins) i maxa ?3 3 ma 26 maximum operating temperature range 10 die junction temperature t j t l 150.0 o c 27 storage temperature range t stg ?55.0 150.0 o c
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 5 3.2 thermal characteristics the shaded rows in the following table indicat e information specific to a four-layer board. 28 maximum solder temperature 11 lead free (pb-free) leaded (snpb) t sdr ? ? 260.0 245.0 o c 29 moisture sensitivity level 12 msl ? 3 1 functional operating conditions are given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only , and functional operation at the maxima is not guaranteed. stress beyond any of the list ed maxima can affect device reliability or cause permanent damage to the device. 2 1.5 v 10% for proper operation. this parameter is specified at a maximum junction temperature of 150 o c. 3 all functional non-supply i/o pins are clamped to v ss and v dde , or v ddeh . 4 ac signal overshoot and undershoot of up to 2.0 v of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 5 internal structures hold the voltage greater than ?1.0 v if the injection current limit of 2 ma is met. keep the negative dc voltage greater than ?0.6 v on sinb during the internal power-on reset (por) state. 6 internal structures hold the input voltage less than the maximum voltage on all pads powered by v ddeh supplies, if the maximum injection current specification is met (2 ma for all pins) and v ddeh is within the operating voltage specifications. 7 internal structures hold the input voltage less than the maximum voltage on all pads powered by v dde supplies, if the maximum injection current specification is met (2 ma for all pins) and v dde is within the operating voltage specifications. 8 total injection current for all pins (including bot h digital and analog) must not exceed 25 ma. 9 total injection current for all analog input pins must not exceed 15 ma. 10 lifetime operation at these specif ication limits is not guaranteed. 11 moisture sensitivity profile per ipc/jedec j-std-020d. 12 moisture sensitivity per jedec test method a112. table 3. mpc5561 thermal characteristics (preliminary values) spec mpc5561 thermal characteristic symbol 324 pbga unit 1 junction to ambient 1, 2 , natural convection (one-layer board) 1 junction temperature is a function of on-ch ip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of othe r components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. r ja 29 c/w 2 junction to ambient 1, 3 , natural convection (four-layer board 2s2p) 3 per jedec jesd51-6 with the board horizontal. r ja 19 c/w 3 junction to ambient (@200 ft./min., one-layer board) r jma 22 c/w 4 junction to ambient (@200 ft./min., four-layer board 2s2p) r jma 16 c/w 5 junction to board (four-layer board 2s2p) 4 4 thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r jb 10 c/w 6 junction to case 5 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) wit h the cold plate temperature us ed for the case temperature. r jc 7c/w 7 junction to package top, natural convection 6 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. jt 2c/w table 2. absolute maximum ratings 1 (continued) spec characteristic symbol min. max. unit
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 6 3.2.1 general notes for specifications at maximum junction temperature an estimation of the device junction temperature, t j , can be obtained from the equation: t j = t a + (r ja p d ) where: t a = ambient temperature for the package ( o c) r ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on the jedec jesd51 series of standards to provide consistent values for estimations and comparisons. the difference betw een the values determined for the single-layer (1s) board compared to a four-layer boa rd that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal re sistance is not a constant . the thermal resistance depends on the: ? construction of the applicati on board (number of planes) ? effective size of the board which cools the component ? quality of the thermal and elec trical connections to the planes ? power dissipated by adjacent components connect all the ground and powe r balls to the resp ective planes with one via pe r ball. using fewer vias to connect the package to the planes reduces the thermal performance. thinner planes also reduce the thermal performance. when the clearance between the vias le ave the planes virtually disconnected, the thermal performance is also greatly reduced. as a general rule, the value obtaine d on a single-layer board is within the normal range for the tightly packed printed circuit board. the valu e obtained on a board with the intern al planes is usually within the normal range if the application board has: ? one oz. (35 micron nominal thickness) internal planes ? components are well separated ? overall power dissipation on the board is less than 0.02 w/cm 2 the thermal performance of any component depe nds on the power dissipation of the surrounding components. in addition, th e ambient temperature varies widely wi thin the application. for many natural convection and especially closed box applications, the board temperatur e at the perimeter (edge) of the package is approximately the same as the local ai r temperature near the device. specifying the local ambient conditions explicitly as the board temperatur e provides a more precise description of the local ambient conditions that determine the temperature of the device.
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 7 at a known board temperature, th e junction temperature is estima ted using the following equation: t j = t b + (r jb p d ) where: t j = junction temperature ( o c) t b = board temperature at the package perimeter ( o c/w) r jb = junction-to-board thermal resistance ( o c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the air doe s not factor into the calcu lation, an acceptable value for the junction temperature is predictable. ensure th e application board is similar to the thermal test condition, with the component soldered to a board with internal planes. the thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient th ermal resistance: r ja = r jc + r ca where: r ja = junction-to-ambient thermal resistance ( o c/w) r jc = junction-to-case thermal resistance ( o c/w) r ca = case-to-ambient thermal resistance ( o c/w) r jc is device related and is not affected by other fact ors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ca . for example, change the air flow around the device, add a heat sink, change the mounti ng arrangement on the printed circui t board, or change the thermal dissipation on the printed circuit board surrounding th e device. this descripti on is most useful for packages with heat sinks where 90% of the heat flow is through th e case to heat sink to ambient. for most packages, a better model is required. a more accurate two-resistor th ermal model can be constructed fr om the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case ther mal resistance describes when using a heat sink or where a s ubstantial amount of heat is dissipat ed from the top of the package. the junction-to-board thermal resistan ce describes the thermal performanc e when most of the heat is conducted to the printed circuit board. this model can be used to generate si mple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of the devi ce in the application on a prototype board, use the thermal characterization parameter ( jt ) to determine the junction temperature by measuring the temperature at the top center of the p ackage case using the following equation: t j = t t + ( jt p d ) where: t t = thermocouple temperature on top of the package ( o c) jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured in compliance with the je sd51-2 specification using a 40-gauge type t thermoc ouple epoxied to the top center of the package case. position the thermocouple
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 8 so that the thermocouple junction rests on the package. place a smal l amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. place the thermocouple wire flat against the package case to avoid m easurement errors caused by the co oling effects of the thermocouple wire. references: semiconductor equipment and materials inte rnational 805 east middlefield rd. mountain view, ca., 94043 (415) 964-5111 mil-spec and eia/jesd (jedec) spec ifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . ? 1. c.e. triplett and b. joiner, ?an experime ntal characterization of a 272 pbga within an automotive engine controller module,? pr oceedings of semitherm, san diego, 1998, pp. 47?54. ? 2. g. kromann, s. shidore, and s. addison, ?thermal modeling of a pbga for air-cooled applications,? electr onic packaging and production, pp. 53?58, march 1998. ? 3. b. joiner and v. adams, ?measurement and si mulation of junction to bo ard thermal resistance and its application in ther mal modeling,? proceedings of semitherm, san diego, 1999, pp. 212?220. 3.3 package the mpc5561 is available in packaged form. read the package options in section 2, ?ordering information.? refer to section 4, ?mechanicals,? for pinouts and package drawings. 3.4 emi (electromagnetic interference) characteristics table 4. emi testing specifications 1 1 emi testing and i/o port waveforms per sae j1752/3 issued 19 95-03. qualification testing was performed on the mpc5554 and applied to the mpc5500 family as generic emi performance data. spec characteristic minimum typical maximum unit 1 scan range 0.15 ? 1000 mhz 2 operating frequency ? ? f max mhz 3v dd operating voltages ? 1.5 ? v 4v ddsyn , v rc33 , v dd33 , v flash , v dde operating voltages ? 3.3 ? v 5v pp , v ddeh , v dda operating voltages ? 5.0 ? v 6 maximum amplitude ? ? 14 2 32 3 2 measured with the single-chip emi program. 3 measured with the expanded emi program. dbuv 7 operating temperature ? ? 25 o c
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 9 3.5 esd (electromagnetic stat ic discharge) characteristics 3.6 voltage regulator controller (v rc ) and power-on reset (por) electrical specifications the following table lists the v rc and por electrical specifications: table 5. esd ratings 1, 2 1 all esd testing conforms to cdf-aec -q100 stress test qualification for automotive grade integrated circuits. 2 device failure is defined as: ?if after exposure to esd pulses, the device does not meet the device specification requirements, which includes the complete dc parametric and function al testing at room temper ature and hot temperature. characteristic symbol value unit esd for human body model (hbm) 2000 v hbm circuit description r1 1500 c100 pf esd for field induced charge model (fdcm) 500 (all pins) v 750 (corner pins) number of pulses per pin: positive pulses (hbm) negative pulses (hbm) ? ? 1 1 ? ? interval of pulses ? 1 second table 6. vrc/por electr ical specifications spec characteristic symbol min. max. units 11.5 v (v dd ) por 1 negated (ramp up) asserted (ramp down) v por15 1.1 1.1 1.35 1.35 v 23.3 v (v ddsyn ) por 1 asserted (ramp up) negated (ramp up) asserted (ramp down) negated (ramp down) v por33 0.0 2.0 2.0 0.0 0.30 2.85 2.85 0.30 v 3 reset pin supply (v ddeh6 ) por 1, 2 negated (ramp up) asserted (ramp down) v por5 2.0 2.0 2.85 2.85 v 4 v rc33 voltage before v rc allows the pass transistor to start turning on v trans_start 1.0 2.0 v 5 when v rc allows the pass transistor to completely turn on 3, 4 v trans_on 2.0 2.85 v 6 when the voltage is greater than the voltage at which the v rc keeps the 1.5 v supply in regulation 5, 6 v vrc33reg 3.0 ? v current can be sourced ? 40 o c11.0?ma 7 by v rcctl at tj: 25 o ci vrcctl 7 9.0 ? ma 150 o c 7.5 ? ma 8 voltage differential during power up such that: v dd33 can lag v ddsyn or v ddeh6 , before v ddsyn and v ddeh6 reach the v por33 and v por5 minimums respectively. v dd33_lag ?1.0v
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 10 3.7 power-up/down sequencing power sequencing between th e 1.5 v power supply and v ddsyn or the reset power supplies is required if using an external 1.5 v power supply with v rc33 tied to ground (gnd). to avoid power-sequencing, v rc33 must be powered up within the specified operati ng range, even if the on-chip voltage regulator controller is not used. refer to section 3.7.2, ?power-up sequence (vrc33 grounded) , ? and section 3.7.3, ?power-down sequence (vrc33 grounded) . ? power sequencing requires that v dd33 must reach a certain voltage where the values are read as ones before the por signal negates. refer to section 3.7.1, ?input value of pins during por dependent on vdd33 . ? although power sequencing is not required between v rc33 and v ddsyn during power up, v rc33 must not lead v ddsyn by more than 600 mv or lag by more than 100 mv for the v rc stage turn-on to operate within specification. higher spikes in the emitte r current of the pass transistor occur if v rc33 leads or lags v ddsyn by more than these amounts. the value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. furthermore, when all of the pors negate, the system clock starts to toggle, adding another large increase of the current consumed by v rc33 . if v rc33 lags v ddsyn by more than 100 mv, the increase in current consumed can drop v dd low enough to assert the 1.5 v por again. oscillations are possible when the 1.5 v por asserts and stops the syst em clock, causing the voltage on v dd to rise until the 1.5 v por negates again. all osci llations stop when v rc33 is powered sufficiently. 9 absolute value of slew rate on power supply pins ? ? 50 v/ms 10 required gain at tj: i dd i vrcctl (@ f sys = f max ) 6 , 7 , 8, 9 ? 40 o c beta 10 60 ? ? 25 o c 65 ?? 150 o c 85 500 ? 1 on power up, assert reset before v por15 , v por33 , and v por5 negate (internal por). reset must remain asserted until the power supplies are within the operating conditions as specified in ta bl e 9 dc electrical specifications . on power down, assert reset before any power supplies fall outside the operating conditions and until the internal por asserts. 2 v il_s ( ta b l e 9 , spec15) is guaranteed to scale with v ddeh6 down to v por5 . 3 supply full operating current for the 1.5 v supp ly when the 3.3 v supply reaches this range. 4 it is possible to reach the current limit during ramp up?do not treat this event as short circuit current. 5 at peak current for device. 6 requires compliance with freescale?s recommended board r equirements and transistor recommendations. board signal traces/routing from the v rcctl package signal to the base of the external pa ss transistor and between the emitter of the pass transistor to the v dd package signals must have a maximum of 100 nh inductance and minimal resistance (less than 1 ). v rcctl must have a nominal 1 f phase compensation capacitor to ground. v dd must have a 20 f (nominal) bulk capacitor (greater than 4 f over all conditions, including lifetime). place high-frequency bypass capacitors consisting of eight 0.01 f, two 0.1 f, and one 1 f capacitors around the package on the v dd supply signals. 7 i vrcctl is measured at the following conditions: v dd = 1.35 v, v rc33 = 3.1 v, v vrcctl = 2.2 v. 8 refer to ta b l e 1 for the maximum operating frequency. 9 values are based on i dd from high-use applications as explained in the i dd electrical specification. 10 represents the worst-case external transistor beta. it is measured on a per-part basis and calculated as (i dd i vrcctl ). table 6. vrc/por electrical specifications (continued) spec characteristic symbol min. max. units
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 11 when powering down, v rc33 and v ddsyn have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. wh en not powering up or down, no delta between v rc33 and v ddsyn is required for the v rc to operate within specification. there are no power up/down sequencing requirements to prevent issues su ch as latch-up, excessive current spikes, and so on. therefore, the state of the i/o pins during power up and power down varies depending on which supplies are powered. table 7 gives the pin state for the sequence cases fo r all pins with pad type pad_fc (fast type). table 8 gives the pin state for the sequence cases for a ll pins with pad type pad_mh (medium type) and pad_sh (slow type). the values in table 7 and table 8 do not include the effect of the weak-pull devices on the output pins during power up. before exiting the internal por state, the voltage on the pins goes to high-impe dance until por negates. when the internal por negates, th e functional state of the signal dur ing reset applies and the weak-pull devices (up or down) are enab led as defined in the device reference manual . if v dd is too low to correctly propagate the logic signals , the weak-pull devices can pull the signals to v dde and v ddeh . to avoid this condition, minimize the ramp time of the v dd supply to a time period less than the time required to enable the external circ uitry connected to the device outputs. 3.7.1 input value of pins during por dependent on v dd33 when powering up the device, v dd33 must not lag the latest v ddsyn or reset power pin (v ddeh6 ) by more than the v dd33 lag specification listed in table 6 , spec 8. this avoids accidentally selecting the bypass clock mode because the internal versions of pllcfg[0:1] and rstcfg are not powered and table 7. pin status for fast pads during the power sequence v dde v dd33 v dd por pin status for fast pad output driver pad_fc (fast) low ? ? asserted low v dde low low asserted high v dde low v dd asserted high v dde v dd33 low asserted high impedance (hi-z) v dde v dd33 v dd asserted hi-z v dde v dd33 v dd negated functional table 8. pin status for medium and slow pads during the power sequence v ddeh v dd por pin status for medium and slow pad output driver pad_mh (medium) pad_sh (slow) low ? asserted low v ddeh low asserted high impedance (hi-z) v ddeh v dd asserted hi-z v ddeh v dd negated functional
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 12 therefore cannot read the defaul t state when por negates. v dd33 can lag v ddsyn or the reset power pin (v ddeh6 ), but cannot lag both by more than the v dd33 lag specification. this v dd33 lag specification applies during power up only. v dd33 has no lead or lag requirements when powering down. 3.7.2 power-up sequence (v rc33 grounded) the 1.5 v v dd power supply must rise to 1.35 v before the 3.3 v v ddsyn power supply and the reset power supply rises above 2.0 v. this ensures that di gital logic in the pll fo r the 1.5 v power supply does not begin to operate below the spec ified operation range lower limit of 1.35 v. because the internal 1.5 v por is disabled, the internal 3.3 v por or the reset power por must hold th e device in reset. since they can negate as low as 2.0 v, v dd must be within specification be fore the 3.3 v por and the reset por negate. figure 2. power-up sequence (v rc33 grounded) 3.7.3 power-down sequence (v rc33 grounded) the only requirement for the power-down sequence with v rc33 grounded is if v dd decreases to less than its operating range, v ddsyn or the reset power must decrease to less than 2.0 v before the v dd power increases to its operating range. this ensures that the digital 1.5 v logic, which is reset only by an ored por and can cause the 1.5 v supply to decrease less than its specification value, resets correctly. v ddsyn and reset power v dd 2.0 v 1.35 v v dd must reach 1.35 v before v ddsyn and the reset power reach 2.0 v
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 13 3.8 dc electrical specifications table 9. dc electrical specifications (t a = t l ? t h ) spec characteristic symbol min max. unit 1 core supply voltage (average dc rms voltage) v dd 1.35 1.65 v 2 input/output supply volt age (fast input/output) 1 v dde 1.62 3.6 v 3 input/output supply voltage (s low and medium input/output) v ddeh 3.0 5.25 v 4 3.3 v input/output buffer voltage v dd33 3.0 3.6 v 5 voltage regulator control input voltage v rc33 3.0 3.6 v 6 analog supply voltage 2 v dda 4.5 5.25 v 8 flash programming voltage 3 v pp 4.5 5.25 v 9 flash read voltage v flash 3.0 3.6 v 10 sram standby voltage 4 v stby 0.8 1.2 v 11 clock synthesizer operating voltage v ddsyn 3.0 3.6 v 12 fast i/o input high voltage v ih_f 0.65 v dde v dde + 0.3 v 13 fast i/o input low voltage v il_f v ss ? 0.3 0.35 v dde v 14 medium and slow i/o input high voltage v ih_s 0.65 v ddeh v ddeh + 0.3 v 15 medium and slow i/o input low voltage v il_s v ss ? 0.3 0.35 v ddeh v 16 fast input hysteresis v hys_f 0.1 v dde v 17 medium and slow i/o input hysteresis v hys_s 0.1 v ddeh v 18 analog input voltage v indc v ssa ? 0.3 v dda + 0.3 v 19 fast output high voltage ( i oh_f = ?2.0 ma ) v oh_f 0.8 v dde ?v 20 slow and medium output high voltage i oh_s = ?2.0 ma i oh_s = ?1.0 ma v oh_s 0.80 v ddeh 0.85 v ddeh ?v 21 fast output low voltage ( i ol_f = 2.0 ma ) v ol_f ?0.2 v dde v 22 slow and medium output low voltage i ol_s = 2.0 ma i ol_s = 1.0 ma v ol_s ? 0.20 v ddeh 0.15 v ddeh v 23 load capacitance (fast i/o) 5 dsc (siu_pcr[8:9] ) = 0b00 = 0b01 = 0b10 = 0b11 c l ? ? ? ? 10 20 30 50 pf pf pf pf 24 input capacitance (digital pins) c in ?7pf 25 input capacitance (analog pins) c in_a ?10pf 26 input capacitance: (shared digital and analog pins an[12]_ma[0]_sds , an[13]_ma[1]_sdo, an[14]_ma[2]_sdi, and an[15]_fck) c in_m ?12pf
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 14 27a operating current 1.5 v supplies @ 135 mhz: 6 8-way cache 7 v dd (including v ddf max current) @1.65 v typical use 8, 9 v dd (including v ddf max current) @1.35 v typical use 8 , 9 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 4-way cache 11 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? 620 440 670 490 610 430 ma ma ma ma ma ma 27b operating current 1.5 v supplies @ 114 mhz: 6 8-way cache 7 v dd (including v ddf max current) @1.65 v typical use 8 , 9 v dd (including v ddf max current) @1.35 v typical use 8 , 9 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 4-way cache 11 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? 590 395 580 390 550 385 ma ma ma ma ma ma 27c operating current 1.5 v supplies @ 82 mhz: 6 8-way cache 7 v dd (including v ddf max current) @1.65 v typical use 8 , 9 v dd (including v ddf max current) @1.35 v typical use 8 , 9 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 4-way cache 11 v dd (including v ddf max current) @1.65 v high use 9 , 10 v dd (including v ddf max current) @1.35 v high use 9 , 10 i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? 485 320 470 315 400 310 ma ma ma ma ma ma 27d refer to figure 3 for an interpolation of this data. 12 i dd_stby @ 25 o c v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v i dd_stby @ 60 o c v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v i dd_stby @ 150 o c (tj) v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby ? ? ? ? ? ? ? ? ? 20 30 50 70 100 200 1200 1500 2000 a a a a a a a a a 28 operating current 3.3 v supplies @ f max mhz v dd33 13 i dd_33 ? 2 + (values derived from procedure of footnote 13 ) ma v flash i vflash ?10ma v ddsyn i ddsyn ?15ma table 9. dc electrical specifications (t a = t l ? t h ) (continued) spec characteristic symbol min max. unit
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 15 29 operating current 5.0 v supplies (12 mhz adclk): v dda (v dda0 + v dda1 ) analog reference supply current (v rh , v rl ) v pp i dd_a i ref i pp ? ? ? 20.0 1.0 25.0 ma ma ma 30 operating current v dde supplies: 14 v ddeh1 v dde2 v dde3 v ddeh4 v dde5 v ddeh6 v dde7 v ddeh8 v ddeh9 i dd1 i dd2 i dd3 i dd4 i dd5 i dd6 i dd7 i dd8 i dd9 ? ? ? ? ? ? ? ? ? refer to footnote 14 ma ma ma ma ma ma ma ma ma 31 fast i/o weak pullup current 15 1.62?1.98 v 2.25?2.75 v 3.00?3.60 v i act_f 10 20 20 110 130 170 a a a fast i/o weak pulldown current 15 1.62?1.98 v 2.25?2.75 v 3.00?3.60 v 10 20 20 100 130 170 a a a 32 slow and medium i/o weak pullup/down current 15 3.0?3.6 v 4.5?5.5 v i act_s 10 20 150 170 a a 33 i/o input leakage current 16 i inact_d ?2.5 2.5 a 34 dc injection current (per pin) i ic ?2.0 2.0 ma 35 analog input current, channel off 17 i inact_a ?150 150 na 35a analog input current, shared analog / digital pins (an[12], an[13], an[14], an[15]) i inact_ad ?2.5 2.5 a 36 v ss to v ssa differential voltage 18 v ss ? v ssa ?100 100 mv 37 analog reference low voltage v rl v ssa ? 0.1 v ssa + 0.1 v 38 v rl differential voltage v rl ? v ssa ?100 100 mv 39 analog reference high voltage v rh v dda ? 0.1 v dda + 0.1 v 40 v ref differential voltage v rh ? v rl 4.5 5.25 v 41 v sssyn to v ss differential voltage v sssyn ? v ss ?50 50 mv 42 v rcvss to v ss differential voltage v rcvss ? v ss ?50 50 mv 43 v ddf to v dd differential voltage v ddf ? v dd ?100 100 mv 43a v rc33 to v ddsyn differential voltage v rc33 ? v ddsyn ?0.1 0.1 19 v 44 analog input differential signal range (with common mode 2.5 v) v idiff ?2.5 2.5 v table 9. dc electrical specifications (t a = t l ? t h ) (continued) spec characteristic symbol min max. unit
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 16 45 operating temperature ra nge, ambient (packaged) t a = (t l to t h )t l t h c 46 slew rate on power-supply pins ? ? 50 v/ms 1 v dde2 and v dde3 are limited to 2.25?3.6 v only if ebts = 0; v dde2 and v dde3 have a range of 1.6?3.6 v if ebts = 1. 2 | v dda0 ? v dda1 | must be < 0.1 v. 3 v pp can drop to 3.0 v during read operations. 4 if standby operation is not required, connect v stby to ground. 5 applies to clkout, external bus pins, and nexus pins. 6 maximum average rms dc current. 7 eight-way cache enabled (l1csr0[corg] = 0b0). 8 average current measured on automotive benchmark. 9 peak currents can be higher on specialized code. 10 high-use current measured while running optimized spe asse mbly code with all code and data 100% locked in cache (0% miss rate) with all channels of the emios running autonomously, plus the edma transferring data continuously from sram to sram. higher currents are possible if an ?idle? loop that crosses ca che lines is run from cache. write code to avoid this condi tion. 11 four-way cache enabled (l1csr0[corg] = 0b1) or (l1csr0[ corg] = 0b0 with l1csr0[wam] = 0b1, l1csr0[wid] = 0b1111, l1csr0[wdd] = 0b1111, l1csr0[awid] = 0b1, and l1csr0[awdd] = 0b1). 12 figure 3 shows an illustration of the i dd_stby values interpolated for these temperature values. 13 power requirements for the v dd33 supply depend on the frequency of operation, load of all i/o pins, and the voltages on the i/o segments. refer to ta b l e 1 1 for values to calculate the power dissipation for a specific operation. 14 power requirements for each i/o segment ar e dependent on the frequency of operation and load of the i/o pins on a particular i/ o segment, and the voltage of the i/o segment. refer to ta b l e 1 0 for values to calculate power diss ipation for specific operation. the total power consumption of an i/o segment is the sum of th e individual power consumptions for each pin on the segment. 15 absolute value of current, measured at v il and v ih . 16 weak pullup/down inactive. measured at v dde = 3.6 v and v ddeh = 5.25 v. applies to pad types: pad_fc, pad_sh, and pad_mh. 17 maximum leakage occurs at maximum operating temperature. leakage current decreases by approximately one-half for each 8 o c to 12 o c, in the ambient temperature range of 50 o c to 125 o c. applies to pad types: pad_a and pad_ae. 18 v ssa refers to both v ssa0 and v ssa1 . | v ssa0 ? v ssa1 | must be < 0.1 v. 19 up to 0.6 v during power up and power down. table 9. dc electrical specifications (t a = t l ? t h ) (continued) spec characteristic symbol min max. unit
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 17 figure 3 shows an approximate interpolation of the i stby worst-case specification to estimate values at different voltages and temperatures . the vertical li nes shown at 25 c, 60 c, and 150 c in figure 3 are the i dd_stby specifications (27d) listed in table 9 . figure 3. i stby worst-case specifications 3.8.1 i/o pad current specifications the power consumption of an i/o se gment depends on the usage of the pi ns on a particular segment. the power consumption is the sum of al l output pin currents for a segmen t. the output pin current can be calculated from table 10 based on the voltage, frequency, and lo ad on the pin. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 10 . table 10. i/o pad average dc current (t a = t l ? t h ) 1 spec pad type symbol frequency (mhz) load 2 (pf) voltage (v) drive select / slew rate control setting current (ma) 1 slow i drv_sh 25 50 5.25 11 8.0 210505.25013.2 3 2 50 5.25 00 0.7 4 2 200 5.25 00 2.4 istby vs. junction tem p 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temp (c) ua 0.8v 1.0v 1.2v a
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 18 3.8.2 i/o pad v dd33 current specifications the power consumption of the v dd33 supply dependents on the usage of the pins on all i/o segments. the power consumption is the sum of all input and output pin v dd33 currents for all i/ o segments. the output pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. the input pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all pad_sh and pad_mh pins. use li near scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 11 . 5 medium i drv_mh 50 50 5.25 11 17.3 620505.25016.5 7 3.33 50 5.25 00 1.1 8 3.33 200 5.25 00 3.9 9 fast i drv_fc 66 10 3.6 00 2.8 10 66 20 3.6 01 5.2 11 66 30 3.6 10 8.5 12 66 50 3.6 11 11.0 13 66 10 1.98 00 1.6 14 66 20 1.98 01 2.9 15 66 30 1.98 10 4.2 16 66 50 1.98 11 6.7 17 56 10 3.6 00 2.4 18 56 20 3.6 01 4.4 19 56 30 3.6 10 7.2 20 56 50 3.6 11 9.3 21 56 10 1.98 00 1.3 22 56 20 1.98 01 2.5 23 56 30 1.98 10 3.5 24 56 50 1.98 11 5.7 25 40 10 3.6 00 1.7 26 40 20 3.6 01 3.1 27 40 30 3.6 10 5.1 28 40 50 3.6 11 6.6 29 40 10 1.98 00 1.0 30 40 20 1.98 01 1.8 31 40 30 1.98 10 2.5 32 40 50 1.98 11 4.0 1 these values are estimates from simulation and ar e not tested. currents apply to output pins only. 2 all loads are lumped. table 10. i/o pad average dc current (t a = t l ? t h ) 1 spec pad type symbol frequency (mhz) load 2 (pf) voltage (v) drive select / slew rate control setting current (ma)
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 19 table 11. v dd33 pad average dc current (t a = t l ? t h ) 1 1 these values are estimated from simulation and not tested. currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. spec pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. v dd33 (v) v dde (v) drive select current (ma) inputs 1slowi 33_sh 66 0.5 3.6 5.5 na 0.003 2 medium i 33_mh 66 0.5 3.6 5.5 na 0.003 outputs 3 fast i 33_fc 66 10 3.6 3.6 00 0.35 466203.63.6010.53 566303.63.6100.62 666503.63.6110.79 7 66 10 3.6 1.98 00 0.35 8 66 20 3.6 1.98 01 0.44 9 66 30 3.6 1.98 10 0.53 10 66 50 3.6 1.98 11 0.70 11 56 10 3.6 3.6 00 0.30 12 56 20 3.6 3.6 01 0.45 13 56 30 3.6 3.6 10 0.52 14 56 50 3.6 3.6 11 0.67 15 56 10 3.6 1.98 00 0.30 16 56 20 3.6 1.98 01 0.37 17 56 30 3.6 1.98 10 0.45 18 56 50 3.6 1.98 11 0.60 19 40 10 3.6 3.6 00 0.21 20 40 20 3.6 3.6 01 0.31 21 40 30 3.6 3.6 10 0.37 22 40 50 3.6 3.6 11 0.48 23 40 10 3.6 1.98 00 0.21 24 40 20 3.6 1.98 01 0.27 25 40 30 3.6 1.98 10 0.32 26 40 50 3.6 1.98 11 0.42
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 20 3.9 oscillator and fmpll electrical characteristics table 12. fmpll electrical specifications (v ddsyn = 3.0?3.6 v; v ss = v sssyn = 0.0 v; t a = t l to t h ) spec characteristic symb ol minimum maximum unit 1 pll reference frequency range: 1 crystal reference (20) 2 crystal reference (40) 3 external reference (20) 2 external reference (40) 3 dual controller (1:1 mode) f ref_crystal f ref_crystal f ref_ext f ref_ext f ref_1:1 8 > 20 8 > 20 24 20 40 20 40 f sys 2 mhz 2 system frequency 4 f sys f ico ( min ) 2 rfd f max 5 mhz 3 system clock period t cyc ?1 f sys ns 4 loss of reference frequency 6 f lor 100 1000 khz 5 self-clocked mode (scm) frequency 7 f scm 7.4 17.5 mhz 6 extal input high voltage crystal mode 8 all other modes [dual controller (1:1), bypass, external reference] v ihext v ihext v xtal + 0.4 v (v dde5 2) + 0.4 v ? ? v v 7 extal input low voltage crystal mode 9 all other modes [dual controller (1:1), bypass, external reference] v ilext v ilext ? ? v xtal ? 0.4 v (v dde5 2) ? 0.4 v v v 8xtal current 10 i xtal 26ma 9 total on-chip stray capacitance on xtal c s_xtal ?1.5pf 10 total on-chip stray capacitance on extal c s_extal ?1.5pf 11 crystal manufacturer?s recommended capacitive load c l refer to crystal specification refer to crystal specification pf 12 discrete load capacitance to connect to extal c l_extal ? (2 c l ) ? c s_extal ? c pcb_extal 11 pf 13 discrete load capacitance to connect to xtal c l_xtal ? (2 c l ) ? c s_xtal ? c pcb_xtal 11 pf 14 pll lock time 12 t lpll ? 750 s 15 dual controller (1:1) clock skew (between clkout and extal) 13, 14 t skew ?2 2 ns 16 duty cycle of reference t dc 40 60 % 17 frequency unlock range f ul ?4.0 4.0 % f sys 18 frequency lock range f lck ?2.0 2.0 % f sys
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 21 19 clkout period jitter, measured at f sys max: 15, 16 peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over a 2 ms interval) c jitter ? ? 5.0 0.01 % f clkout 20 frequency modulation range limit 17 (do not exceed f sys maximum) c mod 0.8 2.4 %f sys 21 ico frequency f ico = [ f ref_crystal (mfd + 4) ] (prediv + 1) 18 f ico = [ f ref_ext (mfd + 4) ] (prediv + 1) f ico 48 f max mhz 22 predivider output frequency (to pll) f prediv 420 19 mhz 1 nominal crystal and external reference values are worst-case not more than 1%. the device operates correctly if the frequency remains within 5% of the specification limit. this tolerance r ange allows for a slight frequency drift of the crystals over t ime. the designer must thoroughly understand the drift margin of the source clock. 2 the 8?20 mhz crystal or external reference values have pllcfg[2] pulled low. 3 the 20?40 mhz crystal and external reference values have pllc fg[2] pulled high, and the minimum frequency must be greater than 20 mhz. use the 8?20 mhz setting (pllcfg[2] pulled low) if a 20 mhz crystal or external reference is required. to exit reset when using 40 mhz, set pllcfg[2] to 1. 4 all internal registers retain data at 0 hz. 5 up to the maximum frequency rating of the device (refer to ta b l e 1 ). 6 loss of reference frequency is defined as the reference frequency detected internally, which transitions the pll into self-cloc ked mode. 7 the pll operates at self-clocked mode (scm) frequency when the reference frequency falls below f lor . scm frequency is measured on the clkout ball wit h the divider set to divide-b y-two of the system clock. note: in scm, the mfd and prediv have no effect and the rfd is bypassed. 8 use the extal input high voltage parameter when using the fl excan oscillator in crystal mode (no quartz crystals or resonators). (v extal ? v xtal ) must be 400 mv for the oscillator?s compar ator to produce the output clock. 9 use the extal input low voltage parameter when using the flexcan oscillator in crystal mode (no quartz crystals or resonators). (v xtal ?v extal ) must be 400 mv for the oscillator?s compar ator to produce the output clock. 10 i xtal is the oscillator bias curr ent out of the xtal pin with both extal and xtal pins grounded. 11 c pcb_extal and c pcb_xtal are the measured pcb stray capacitances on extal and xtal, respectively. 12 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). from power up with crysta l oscillator reference, the lock time also includes the crystal startup time. 13 pll is operating in 1:1 pll mode. 14 v dde = 3.0?3.6 v. 15 jitter is the average deviation from t he programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device po wered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the jitter percentage for a given interval. clkout divider is set to divide-by-two. 16 values are with frequency modulation disabled. if frequency m odulation is enabled, jitter is the sum of (jitter + cmod). 17 modulation depth selected must not result in f sys value greater than the f sys maximum specified value. 18 f sys = f ico (2 rfd ) 19 maximum value for dual controller (1:1) mode is (f max 2) with the predivider set to 1 (fmpll_syncr[prediv] = 0b001). table 12. fmpll electrical specifications (continued) (v ddsyn = 3.0?3.6 v; v ss = v sssyn = 0.0 v; t a = t l to t h ) spec characteristic symb ol minimum maximum unit
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 22 3.10 eqadc electrical characteristics table 13. eqadc conversion specifications ( t a = t l to t h ) spec characteristic symbol minimum maximum unit 1 adc clock (adclk) frequency 1 1 conversion characteristics vary with f adclk rate. reduced conversion accuracy occurs at maximum f adclk rate. the maximum value is based on 800 ks/s and the minimum value is based on 20 mhz oscillator clock frequency divided by a maximum 16 factor. f adclk 112mhz 2 conversion cycles differential single ended cc 13 + 2 (15) 14 + 2 (16) 13 + 128 (141) 14 + 128 (142) adclk cycles 3 stop mode recovery time 2 2 stop mode recovery time begins when the adc control register enable bits are set until the adc is ready to perform conversions. t sr 10 ? s 4 resolution 3 3 at v rh ? v rl = 5.12 v, one least significant bit (lsb) = 1.25, mv = one count. ?1.25 ? mv 5 inl: 6 mhz adc clock inl6 ?4 4 counts 3 6 inl: 12 mhz adc clock inl12 ?8 8 counts 7 dnl: 6 mhz adc clock dnl6 ?3 4 4 guaranteed 10-bit mono tonicity. 3 4 counts 8 dnl: 12 mhz adc clock dnl12 ?6 4 6 4 counts 9 offset error with calibration offwc ?4 5 5 the absolute value of the offset error without calibration 100 counts. 4 5 counts 10 full-scale gain error with calibration gainwc ?8 6 6 the absolute value of the full scale gain error without calibration 120 counts. 8 6 counts 11 disruptive input injection current 7, 8, 9, 10 7 below disruptive current conditions, the channel being stressed has conversion values of: 0x3ff for analog inputs greater than v rh , and 0x000 for values less than v rl . this assumes that v rh v dda and v rl v ssa due to the presence of the sample amplifier. other channels are not af fected by non-disruptive conditions. 8 exceeding the limit can cause a conversion error on both stressed and unstressed channels. transi tions within the limit do not affect device reliability or cause permanent damage. 9 input must be current limited to the val ue specified. to determine the value of th e required current-limiting resistor, calcula te resistance values using v posclamp = v dda + 0.5 v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 10 this condition applies to two adjacent pads on the internal pad. i inj ?1 1 ma 12 incremental error due to injection current. all channels are 10 k < rs <100 k channel under test has rs = 10 k , i inj = i injmax , i injmin e inj ?4 4 counts 13 total unadjusted error (tue) for single ended conversions with calibration 11, 12, 13, 14, 15 11 the tue specification is always less t han the sum of the inl, dn l, offset, and gain errors due to canceling errors. 12 tue does not apply to differential conversions. 13 measured at 6 mhz adc clock. tue with a 12 mhz adc clock is: ?16 counts < tue < 16 counts. 14 tue includes all internal device errors such as internal reference variation (75% ref, 25% ref). 15 depending on the input impedance, the analog input leakage current ( ta b l e 9 . dc electrical specifications , spec 35a) can affect the actual tue measured on analog channels an[12], an[13], an[14], an[15]. tue ?4 4 counts
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 23 3.11 h7fa flash memory electrical characteristics spec table 14. flash program and erase specifications (t a = t l to t h ) spec flash program characte ristic symbol min. typical 1 1 typical program and erase times are calculated at 25 o c operating temperature using nominal supply values. initial max. 2 2 initial factory condition: 100 program/erase cycles, 25 o c, using a typical supply voltage measured at a minimum system frequency of 80 mhz. max. 3 3 the maximum erase time occurs after the specified number of program/erase cycles. this maximum value is characterized but not guaranteed. unit 3 doubleword (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. t dwprogram ? 10 ? 500 s 4 page program time 4 t pprogram ? 22 44 5 5 page size is 256 bits (8 words). 500 s 7 16 kb block pre-program and erase time t 16kpperase ? 265 400 5000 ms 9 48 kb block pre-program and erase time t 48kpperase ? 345 400 5000 ms 10 64 kb block pre-program and erase time t 64kpperase ? 415 500 5000 ms 8 128 kb block pre-program and erase time t 128kpperase ? 500 1250 7500 ms 11 minimum operating frequency for program and erase operations 6 6 the read frequency of the flash can range up to the maxi mum operating frequency. there is no minimum read frequency condition. ?25???mhz table 15. flash eeprom module life (t a = t l to t h ) spec characteristic symbol min. typical 1 1 typical endurance is evaluated at 25 o c. product qualification is performed to the minimum specification. for additional information on the freescale definition of typica l endurance, refer to engineering bulletin eb619 typical endurance for nonvolatile memory . unit 1a number of program/erase cycles per block for 16 kb, 48 kb, and 64 kb blocks over the operating temperature range (t j ) p/e 100,000 ? cycles 1b number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) p/e 1000 100,000 cycles 2 data retention blocks with 0? 1,000 p/e cycles blocks with 1,00 1?100,000 p/e cycles retention 20 5 ? ? years
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 24 table 16 shows the flash_biu settings versus frequency of operation. refer to the device reference manual for definitions of these bit fields. 3.12 ac specifications 3.12.1 pad ac specifications table 16. flash_biu settings vs. frequency of operation 1 1 illegal combinations exist. use entries from the same row in this table. maximum frequency (mhz) apc rwsc wwsc dpfen 2 2 for maximum flash performance, set to 0b11. ipfen 2 pflim 3 3 for maximum flash performance, set to 0b110. bfen 4 4 for maximum flash performance, set to 0b1. up to and including 82 mhz 5 5 82 mhz parts allow for 80 mhz system clock + 2% frequency modulation (fm). 0b001 0b001 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 up to and including 102 mhz 6 6 102 mhz parts allow for 100 mhz system clock + 2% fm. 0b001 0b010 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 up to and including 135 mhz 7 7 135 mhz parts allow for 132 mhz system clock + 2% fm. 0b010 0b011 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 default setting after reset 0b111 0b111 0b11 0b00 0b00 0b000 0b0 table 17. pad ac specifications (v ddeh = 5.0 v, v dde = 1.8 v) 1 spec pad src / dsc (binary) out delay 2, 3, 4 (ns) rise / fall 4 , 5 (ns) load drive (pf) 1 slow high voltage (sh) 11 26 15 50 82 60 200 01 75 40 50 137 80 200 00 377 200 50 476 260 200 2 medium high voltage (mh) 11 16 8 50 43 30 200 01 34 15 50 61 35 200 00 192 100 50 239 125 200
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 25 3fast 00 3.1 2.7 10 01 2.5 20 10 2.4 30 11 2.3 50 4 pullup/down (3.6 v max) ? ? 7500 50 5 pullup/down (5.5 v max) ? ? 9000 50 1 these are worst-case values that are estimated from simulati on (not tested). the values in the table are simulated at: v dd = 1.35?1.65 v; v dde = 1.62?1.98 v; v ddeh = 4.5?5.25 v; v dd33 and v ddsyn = 3.0?3.6 v; and t a =t l to t h . 2 this parameter is supplied for reference and is guaranteed by design (not tested). 3 the output delay is shown in figure 4 . to calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay. 4 the output delay and rise and fall are measured to 20% or 80% of the respective signal. 5 this parameter is guaranteed by characterization rather than 100% tested. table 18. derated pad ac specifications (v ddeh = 3.3 v, v dde = 3.3 v) 1 1 these are worst-case values that are es timated from simulation (not tested). the values in the table are simulated at: v dd = 1.35?1.65 v; v dde = 3.0?3.6 v; v ddeh = 3.0?3.6 v; v dd33 and v ddsyn = 3.0?3.6 v; and t a = t l to t h . spec pad src/dsc (binary) out delay 2, 3, 4 (ns) 2 this parameter is supplied for referenc e and guaranteed by design (not tested). rise / fall 3 , 5 (ns) load drive (pf) 1 slow high voltage (sh) 11 39 23 50 120 87 200 01 101 52 50 188 111 200 00 507 248 50 597 312 200 2 medium high voltage (mh) 11 23 12 50 64 44 200 01 50 22 50 90 50 200 00 261 123 50 305 156 200 3fast 00 3.2 2.4 10 01 2.2 20 10 2.1 30 11 2.1 50 4 pullup/down (3.6 v max) ? ? 7500 50 5 pullup/down (5.5 v max) ? ? 9500 50 table 17. pad ac specifications (v ddeh = 5.0 v, v dde = 1.8 v) 1 (continued) spec pad src / dsc (binary) out delay 2, 3, 4 (ns) rise / fall 4 , 5 (ns) load drive (pf)
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 26 figure 4. pad output delay 3.13 ac timing 3.13.1 reset and configuration pin timing 3 the output delay, and the rise and fall, are calcul ated to 20% or 80% of the respective signal. 4 the output delay is shown in figure 4 . to calculate the output dela y with respect to the system clock, add a maximum of one system clock to the output delay. 5 this parameter is guaranteed by charac terization rather than 100% tested. table 19. reset and configuration pin timing 1 1 reset timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max. unit 1 reset pulse width t rpw 10 ? t cyc 2 reset glitch detect pulse width t gpw 2?t cyc 3 pllcfg, bootcfg, wkpcfg, rstcfg setup time to rstout valid t rcsu 10 ? t cyc 4 pllcfg, bootcfg, wkpcfg, rstcfg hold time from rstout valid t rch 0?t cyc v dd 2 v oh v ol rising-edge out delay falling-edge pad internal data pad output out delay input signal
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 27 figure 5. reset and configuration pin timing 1 2 reset rstout wkpcfg pllcfg 3 4 bootcfg rstcfg
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 28 3.13.2 ieee 1149.1 interface timing figure 6. jtag test clock input timing table 20. jtag pin ac electrical characteristics 1 1 these specifications apply to jtag boundary scan only. jtag timing specified at: v dde = 3.0?3.6 v and t a = t l to t h . refer to ta b l e 2 1 for nexus specifications. spec characteristic symbol min. max. unit 1 tck cycle time t jcyc 100 ? ns 2 tck clock pulse width (measured at v dde 2) t jdc 40 60 ns 3 tck rise and fall times (40% to 70%) t tckrise ?3ns 4 tms, tdi data setup time t tmss, t tdis 5?ns 5 tms, tdi data hold time t tmsh, t tdih 25 ? ns 6 tck low to tdo data valid t tdov ?20ns 7 tck low to tdo data invalid t tdoi 0?ns 8 tck low to tdo high impedance t tdohz ?20ns 9 jcomp assertion time t jcmppw 100 ? ns 10 jcomp setup time to tck low t jcmps 40 ? ns 11 tck falling-edge to output valid t bsdv ?50ns 12 tck falling-edge to output valid out of high impedance t bsdvz ?50ns 13 tck falling-edge to output high impedance (hi-z) t bsdhz ?50ns 14 boundary scan input valid to tck rising-edge t bsdst 50 ? ns 15 tck rising-edge to boundary scan input invalid t bsdht 50 ? ns tck 1 2 2 3 3
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 29 figure 7. jtag test access port timing figure 8. jtag jcomp timing tck 4 5 6 7 8 tms, tdi tdo tck jcomp 9 10
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 30 figure 9. jtag boundary scan timing tck output signals input signals output signals 11 12 13 14 15
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 31 3.13.3 nexus timing figure 10. nexus output timing table 21. nexus debug port timing 1 1 jtag specifications apply when used for debug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 1.35?1.65 v, v dde = 2.25?3.6 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 30 pf with dsc = 0b10. spec characteristic symbol min. max. unit 1 mcko cycle time t mcyc 1 2 2 the nexus aux port runs up to 82 mhz. set npc_pcr[mcko _div] to divide-by-two if the system frequency is greater than 82 mhz. 8t cyc 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo data valid 3 3 mdo, mseo , and evto data is held valid until the next mcko low cycle occurs. t mdov ?1.5 3.0 ns 4 mcko low to mseo data valid 3 t mseov ?1.5 3.0 ns 5 mcko low to evto data valid 3 t evtov ?1.5 3.0 ns 6 evti pulse width t evtipw 4.0 ? t tcyc 7 evto pulse width t evtopw 1?t mcyc 8 tck cycle time t tcyc 4 4 4 limit the maximum frequency to approximately 16 mhz (v dde = 2.25?3.0 v) or 20 mhz (v dde = 3.0?3.6 v) to meet the timing specification for t jov of [0.2 x t jcyc ] as outlined in the ieee-isto 5001-200 3 specification. ?t cyc 9 tck duty cycle t tdc 40 60 % 10 tdi, tms data setup time t ntdis, t ntmss 8?ns 11 tdi, tms data hold time t ntdih, t ntmsh 5?ns 12 tck low to tdo data valid t jov v dde = 2.25?3.0 v 0 12 ns v dde = 3.0?3.6 v 0 10 ns 13 rdy valid to mcko 5 5 the rdy pin timing is asynchronous to mcko and is guaranteed by design to function correctly. ???? 1 2 3 4 5 mcko mdo mseo evto output data valid
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 32 figure 11. nexus tdi, tms, tdo timing tdo 10 11 tms, tdi 12 tck
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 33 3.13.4 external bus interface (ebi) timing lists the timing information for the external bus interface (ebi). table 22. bus operation timing 1 spec characteristic and description symbol external bus frequency 2, 3 unit notes 40 mhz 56 mhz 66 mhz min. max. min. max. min. max. 1 clkout period t c 24.4 ? 17.5 ? 14.9 ? ns signals are measured at 50% v dde . 2 clkout duty cycle t cdc 45% 55% 45% 55% 45% 55% t c 3 clkout rise time t crt ?? 4 ?? 4 ?? 4 ns 4 clkout fall time t cft ?? 4 ?? 4 ?? 4 ns 5 clkout positive edge to output signal invalid or hi-z (hold time) external bus interface cs [0:3] addr[8:31] data[0:31] 5 bdip oe rd_wr ta tea 6 ts we /be [0:3] 7 t coh 1.0 8 1.5 ? 1.0 8 1.5 ? 1.0 8 1.5 ?ns ebts = 0 ebts = 1 hold time selectable via siu_eccr [ebts] bit. 6 clkout positive edge to output signal valid (output delay) external bus interface cs [0:3] addr[8:31] data[0:31] 5 bdip oe rd_wr ta tea 6 ts we /be [0:3] 7 t cov ? 10.0 8 11.0 ? 7.5 8 8.5 ? 6.0 8 7.0 ns ebts = 0 ebts = 1 output valid time selectable via siu_eccr [ebts] bit.
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 34 figure 12. clkout timing 7 input signal valid to clkout positive edge (setup time) external bus interface addr[8:31] data[0:31] 5 rd_wr ta tea 6 ts t cis 10.0 ? 7.0 ? 5.0 ? ns 8 clkout positive edge to input signal invalid (hold time) external bus interface addr[8:31] data[0:31] 5 rd_wr ta tea 6 ts t cih 1.0 ? 1.0 ? 1.0 ? ns 1 ebi timing specified at: v dde = 1.6?3.6 v (unless stated otherwise); t a = t l to t h ; and cl = 30 pf with dsc = 0b10. 2 speed is the nominal maximum frequency. max. speed is t he maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system cl ock + 2% fm; 114 mhz parts allow fo r 112 mhz system clock + 2% fm; and 135 mhz parts allow for 132 mhz system clock + 2% fm. 3 the external bus is limited to half the speed of the internal bus. 4 refer to fast pad timing in ta bl e 1 7 and ta bl e 1 8 (different values for 1.8 v and 3.3 v). 5 due to pin limitations, the data[16:31] signals are not available on the 324 package. 6 due to pin limitations, the tea signal is not available on the 324 package. 7 due to pin limitations, the we /be [2:3] signals are not available on the 324 package. 8 ebts = 0 timings are tested and valid at v dde = 2.25?3.6 v only; ebts = 1 timings are tested and valid at v dde = 1.6?3.6 v. table 22. bus operation timing 1 (continued) spec characteristic and description symbol external bus frequency 2, 3 unit notes 40 mhz 56 mhz 66 mhz min. max. min. max. min. max. 1 2 2 3 4 clkout v dde 2 vol_f voh_f
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 35 figure 13. synchronous output timing 6 5 5 clkout bus 5 output signal output v dde 2 v dde 2 v dde 2 v dde 2 6 5 output signal v dde 2 6
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 36 figure 14. synchronous input timing 3.13.5 external interrupt timing (irq signals) table 23. external interrupt timing 1 1 irq timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max. unit 1 irq pulse-width low t ipwl 3?t cyc 2 irq pulse-width high t ipwh 3?t cyc 3 irq edge-to-edge time 2 2 applies when irq signals are configured for ri sing-edge or falling-edge events, but not both. t icyc 6?t cyc 7 8 clkout input bus 7 8 input signal v dde 2 v dde 2 v dde 2
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 37 figure 15. external interrupt timing 3.13.6 emios timing figure 16. emios timing table 24. emios timing 1 1 emios timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max. unit 1 emios input pulse width t mipw 4?t cyc 2 emios output pulse width t mopw 1 2 2 this specification does not include the rise and fall times. when calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fi eld (src) in the pad conf iguration register (pcr). ?t cyc irq 1 2 3 1 2 emios output emios input
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 38 3.13.7 dspi timing table 25. dspi timing 1 ? 2 1 all dspi timing specifications use the fastest slew rate (s rc = 0b11) on pad type m or mh. dspi signals using pad types of s or sh have an additional delay based on the slew rate. dspi timing is specified at: v ddeh = 3.0?5.5 v;t a = t l to t h ; and cl = 50 pf with src = 0b11. 2 speed is the nominal maximum frequency. max. speed is th e maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system cl ock + 2% fm; 114 mhz parts allow fo r 112 mhz system clock + 2% fm; and 135 mhz parts allow for 132 mhz system clock + 2% fm. spec characteristic symbol 80 mhz 112 mhz 132 mhz unit min. max. min. max. min. max. 1 sck cycle time 3, 4 3 the minimum sck cycle time restricts the baud rate selection for the given system clock rate. these numbers are calculated based on two mpc55xx devices communicating over a dspi link. 4 the actual minimum sck cycle time is limited by pad performance. t sck 24.4 ns 2.9 ms 17.5 ns 2.1 ms 14.8 ns 1.8 ms ? 2 pcs to sck delay 5 5 the maximum value is programmable in d spi_ctarx[pssck] and dspi_ctarx[cssck]. t csc 23 ? 15 ? 13 ? ns 3 after sck delay 6 6 the maximum value is programmable in dspi_ctarx[pasc] a nd dspi_ctarx[asc]. t asc 22 ? 14 ? 12 ? ns 4 sck duty cycle t sdc (t sck 2) ? 2 ns (t sck 2) + 2 ns (t sck 2) ? 2 ns (t sck 2) + 2 ns (t sck 2) ? 2 ns (t sck 2) + 2 ns ns 5 slave access time (ss active to sout driven) t a ? 25 ? 25 ? 25 ns 6 slave sout disable time (ss inactive to sout hi-z, or invalid) t dis ? 25 ? 25 ? 25 ns 7pcs x to pcss time t pcsc 4?4?4?ns 8pcss to pcs x time t pasc 5?5?5?ns 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 7 master (mtfe = 1, cpha = 1) 7 this number is calculated using the smpl_pt field in dspi_mcr set to 0b10. t sui 20 2 ?4 20 ? ? ? ? 20 2 3 20 ? ? ? ? 20 2 6 20 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 7 master (mtfe = 1, cpha = 1) t hi ?4 7 21 ?4 ? ? ? ? ?4 7 14 ?4 ? ? ? ? ?4 7 12 ?4 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t suo ? ? ? ? 5 25 18 5 ? ? ? ? 5 25 14 5 ? ? ? ? 5 25 13 5 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho ?5 5.5 8 ?5 ? ? ? ? ?5 5.5 4 ?5 ? ? ? ? ?5 5.5 3 ?5 ? ? ? ? ns ns ns ns
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 39 figure 17. dspi classic spi timing?master, cpha = 0 figure 18. dspi classic spi timing?master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1)
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 40 figure 19. dspi classic spi timing?slave, cpha = 0 figure 20. dspi classic spi timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1)
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 41 figure 21. dspi modified transfer format timing?master, cpha = 0 figure 22. dspi modified transfer format timing?master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1)
mpc5561 microcontroller data sheet, rev. 2.0 electrical characteristics freescale semiconductor 42 figure 23. dspi modified transfer format timing?slave, cpha = 0 figure 24. dspi modified transfer format timing?slave, cpha = 1 figure 25. dspi pcs strobe (pcss ) timing last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 7 8 pcss
electrical characteristics mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 43 3.13.8 eqadc ssi timing figure 26. eqadc ssi timing table 26. eqadc ssi ti ming charact eristics spec rating symbol minimum typical maximum unit 2 fck period (t fck = 1 f fck ) 1, 2 1 ss timing specified at v ddeh = 3.0?5.25 v, t a = t l to t h , and cl = 25 pf with src = 0b11. maximum operating frequency varies depending on track delays, master pad delays, and slave pad delays. 2 fck duty cycle is not 50% when it is generated through the division of the system clock by an odd number. t fck 2? 17t sys_clk 3 clock (fck) high time t fckht t sys_clk ? 6.5 ? 9 (t sys_clk + 6.5) ns 4 clock (fck) low time t fcklt t sys_clk ? 6.5 ? 8 (t sys_clk + 6.5) ns 5 sds lead / lag time t sds_ll ?7.5 ? +7.5 ns 6 sdo lead / lag time t sdo_ll ?7.5 ? +7.5 ns 7 eqadc data setup time (inputs) t eq_su 22 ? ? ns 8 eqadc data hold time (inputs) t eq_ho 1? ? ns 1st (msb) 2nd 25th 26th 1st (msb) 2nd 25th 26th 8 7 5 6 4 5 4 2 3 fck sds sdo external device data sample at sdi eqadc data sample at fck falling-edge fck rising-edge
mpc5561 microcontroller data sheet, rev. 2.0 mechanicals freescale semiconductor 44 4 mechanicals 4.1 mpc5561 324 pbga pinouts figure 27 is a pinout for the mpc5561 324 pbga package. figure 27. mpc5561 324 package pinouts vss 1 2 3 4 5 6 7 8 9 10111213141516171819202122 an28 vdd vstby an37 an11 vdda1 an1 an5 vrh vrl an27 an35 vssa0 mdo10 mdo8 vdd vdd33 vss a vdd33 an31 vss vdd an36 an39 an19 an0 an23 an26 an32 vssa0 mdo9 mdo7 mdo4 mdo0 vss vdde7 b an30 vss vdd an8 an17 an21 an3 an7 an22 an25 an33 vdda0 an14 mdo5 mdo2 mdo1 vss vdde7 vdd c an29 vss vdd an38 an10 an18 an2 an6 an24 an15 mdo6 vss vdde7 tck tdi d vdde7 tms tdo test e vdde7 jcomp evti evto f rdy g vss vss vss vss vss vdde7 vss vss vss vss vss vss vss vss vss vss vss vss sinb h vss vdde2 vdde2 vss vss vss soutb pcsb3 pcsb0 pcsb1 j vss vss vss vdde2 vss vss rxdd pcsb4 sckb pcsb2 k vss vss vss vdde2 vss vss pcsb5 pcsc5 pcsc2 pcsc1 l bdip cs1 cs0 pcsb2 txdc txdd vpp m cs2 we1 we0 rxdc txda pcsb3 vflash n rd_wr cntxc rxda rstout p rxdb cnrxc txdb reset r ts t extal u vdde2 vdd xtal v vss vdd vdde2 vdde5 nc vss vdd vrc33 w vss vdd cntxa vdde5 nc vss vdd vdd33 y vss vdd cnrxa vdde5 clkout vss vdd aa vss vdd vdde2 vdde2 pcsc3 pcsc4 vdde5 vss ab a b c d e f g h j k l m n p r t u v 1 2 3 4 5 6 7 8 9 10111213141516171819202122 an9 an20 an16 vssa1 pcsc1 pcsc2 irq13 irq12 irq15 irq 11 irq 10 pdi irq8 pdi data8 pcsb4 pcsb3 pdi pcsb5 pdichn sel2 vddeh 1 frbrx gpio 204 gpio 203 vddeh 10 addr 16 addr 17 addr 18 addr 19 addr 20 addr 21 addr 12 addr 22 addr 23 addr 13 addr 25 addr 31 addr 15 addr 26 addr 24 addr 30 addr 28 addr 27 addr 29 data 0 data 1 data 8 data 3 data 9 data 4 data 13 gpio 206 data 5 data 10 data 11 data 12 data 14 data 15 data 7 emios 6 emios 2 emios 10 emios 15 vddeh 4 emios 12 emios 17 emios 16 emios 14 emios 22 emios 19 emios 18 emios 23 emios 20 emios 21 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk note: no connect. reserved (w18 & y19 are shorted to each other) nc w y aa ab mdo11 an12 an4 ref bypc an13 pcsc3 pcsc4 irq14 irq9 pdi data7 an34 vddeh 9 mdo3 pdi data0 pcsb1 pdifrm gpio 121 pdichn gpio 114 irq7 pdisnr frbtx pdichn sel1 frbtx pdiline valid mcko mseo0 mseo1 cs3 vdd33 ta vdde2 addr 14 vdde2 vdd33 emios 8 vdde2 vdde2 vdde2 gpio 207 data 2 data 6 emios 13 emios 9 emios 5 emios 3 oe emios 11 emios 7 emios 4 emios 1 emios 0 pll cfg2 valid clk en sel0 data5 data6
mechanicals mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 45 4.2 mpc5561 324-pin package dimensions the package drawings of the mpc5561 324-pin tepbga package are shown in figure 28 . figure 28. mpc5561 324 tepbga package
mpc5561 microcontroller data sheet, rev. 2.0 mechanicals freescale semiconductor 46 figure 28. mpc5561 324 tepbga package (continued)
revision history for the mpc5561 data sheet mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 47 5 revision history for the mpc5561 data sheet the history of revisions made to th is data sheet are shown in this s ection. the changes are divided into each revision of this document. the substantive cha nges incorporated in mpc 5561 data sheet rev. 0.0 to produce rev. 1.0 of this doc ument are grouped as follows: ? global and text changes ? table and figure changes within each group, the changes ar e listed in sequential order. 5.1 information changed between revisions 0.0 and 1.0 the following table lists the global changes made throughout the document, as well as substantive changes to text that is not in a table of figure. table 27. global and text changes between rev. 0.0 and rev. 1.0 location description of changes global changes throughout the document ? replaced kilobytes with kb. ? replaced megabytes with mb. section 1, ?overview ?: ? first paragraph: text changed from ?. . . based on the powerpc book e architecture? to ?. . . built on the power architecture embedded technology.? ? second paragraph: changed terminology from powerpc book e architecture to power architecture terminology. ? added new third paragraph about vle feature. ? added new eighth paragraph about the parallel digital interface (pdi). ? paragraph nine: changed ?the mpc5561 has an on-chip 20-channel enhanced queued analog-to-digital converter (eqadc)? to ?. . . has an on-chip 40-channel dual enhanced queued . . .? ? added the sentence preceding ta b l e 1 : ?unless noted in this data sheet, all specifications apply from t l to t h .? sections 3.7.1, 3.7.2 and 3.7.3: reordered sections resulting in the following order and section renumbering: ? section 3.7.1, ?input value of pins during por dependent on vdd33 ,? t he n ? section 3.7.2, ?power-up sequence (vrc33 grounded) ,? then ? section 3.7.3, ?power-down sequence (vrc33 grounded) . section 3.7.1, ?input value of pins during por dependent on vdd33 ,? changed: from: ?to avoid accidentally selecting the bypass clock because pllcfg[0:1] and rstcfg are not treated as ones (1s) when por negates, v dd33 must not lag v ddsyn and the reset pin power (v ddeh6 ) when powering the device by more than the v dd33 lag specification in ta bl e 6 . v dd33 individually can lag either v ddsyn or the reset power pin (v ddeh6 ) by more than the v dd33 lag specification. v dd33 can lag one of the v ddsyn or v ddeh6 supplies, but cannot lag both by more than the v dd33 lag specification. this v dd33 lag specification only applies during power up. v dd33 has no lead or lag requirements when powering down.? to : ?when powering the device, v dd33 must not lag v ddsyn and the reset power pin (v ddeh6 ) by more than the v dd33 lag specification listed in ta b l e 6 . this avoids accidentally selectin g the bypass clock mode because the internal versions of pllcfg[0:1] and rstcfg are not powered and therefore cannot read the default state when por negates. v dd33 can lag v ddsyn or the reset power pin (v ddeh6 ), but cannot lag both by more than the v dd33 lag specification. this v dd33 lag specification only applies during power up. v dd33 has no lead or lag requirements when powering down.?
mpc5561 microcontroller data sheet, rev. 2.0 revision history for the mpc5561 data sheet freescale semiconductor 48 the following table describes the changes ma de to information in tables and figures: section 3.7.1, ?input value of pins during por dependent on vdd33 :? added the following text directly before this section and after ta bl e 8 pin status for medium / slow pads during the power-on sequence : ?the values in ta b l e 7 and ta b l e 8 do not include the effect of the weak pu ll devices on the output pins during power up. before exiting the internal por state, the voltage on the pins goes to high- impedance until por negates. when the internal por negates, the functional stat e of the signal during reset applies and the weak pull devices (up or down) are enabled as defined in the device reference manual . if v dd is too low to correctly propagate the logic signals, the weak-pull devices can pull the signals to v dde and v ddeh . to avoid this condition, minimize the ramp time of the v dd supply to a time period less than the time required to enable the external circuitry connected to the device outputs.? section 3.7.3, ?power-down sequence (vrc33 grounded) ? deleted the underscore in ored_por to become ored por. section 3.13.6, ?etpu timing ? deleted entire section, including table and figure, because the mpc5561 does not have the etpu module. table 28. table and figure changes between rev. 0.0 and 1.0 location description of changes figure 1 mpc5500 family part numbers : ? removed the 2 in the tape and reel designator in both the graphic and in the tape and reel status text. ? changed qualification status by ad ding ?, general market flow? to the m designator, and added an ?s? designator with the description of ?fully spec. qualified, automotive flow. ? changed footnote 1 to read: all devices are ppc5561 , rather than mpc5561 or spc5561, until product qualifications are complete. not all confi gurations are available in the ppc parts. ta bl e 1 orderable part numbers : ? increased the frequency values in the maximum column by 2 ns. ? changed the maximum operating frequency from 132 mhz to 135 mhz. ? reordered rows to group devices by lead-free pa ckage types in descending frequency order, and leaded package types. ? footnote 2: added ?ambient? between ?lowest? and ?operating? and ?highest? and ?operating.? ? changed footnote 3 from ?132 mhz allows only 128 mhz + 2% fm? to ?135 mhz allows for 132 mhz + 2% fm?. table 27. global and text changes between rev. 0.0 and rev. 1.0 (continued) location description of changes
revision history for the mpc5561 data sheet mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 49 ta bl e 2 absolute maximum ratings : ? deleted spec 3, ?flash core voltage.? ? spec 12 ?dc input voltage?: deleted from second line?. . .except for etpub15 and sinb (dspi_b_sin)? leaving v ddeh powered i/o pads. deleted third line ?v ddeh powered by i/o pads (etpub15 and sinb), including the min. and max values of -0.3 and 6.5 respectively, and deleted old footnote 7. ? spec 12 ?dc input voltage?: a dded footnote 8 to second line ?v dde powered i/o pads? that reads: ?internal structures hold the input voltage less than the maximum voltage on all pads powered by the v dde supplies, if the maximum injection current specification is met (s ma for all pins) and v dde is within the operating voltage specifications. ? spec 14, column 2, changed: ?v ss differential voltage? to ?v ss to v ssa differential voltage.? ? spec 15, column 2, changed: ?v dd differential voltage? to ?v dd to v dda differential voltage.? ? spec 21, added the name of the spec, ? v rc33 to v ddsyn differential voltage,? as well as the name and cross reference to ta b l e 9 , dc electrical specification s, to which the spec was moved. ? spec 28 ?maximum solder temperature?: added two sublines: lead free (pbfree) and leaded (snpb) with maxi mum values of 260 c and 245 c respectively. ? footnote 1, added: ?any of? between ?beyond? and ?the listed maxima.? ? deleted footnote 2: ?absolute maximum voltages are currently maximum burn-in voltages. absolute maximum specifications for device stress have not yet been determined.?spec 26 ?maximum operating temperature range?: replaced -40 c with t l . ? footnote 6 (now footnote 5): added the following sent ence to the end, ?keep the negative dc voltage greater than -0.6 v on sinb during the internal power-on reset (por) state.? ta bl e 4 emi testing specifications : ? changed the maximum operating frequency to from 132 to f max . ? footnote 2: deleted ?refer to table 1 for the maximum operating frequency.? ta bl e 5 esd characteristics : added (electromagnetic static discharge) in the table title. ta bl e 6 vcr/por electrical specifications : ? subscript all symbol names that appear after the first underscore character. ? specs 7 and 10: added ?at tj ?at the end of the first line in the second column: characteristic. ? footnote 10: deleted ?preliminary value. final specification pending characterization.? ? added to spec 2: 3.3 v (v ddsyn ) por negated (ramp down) min. 0.0 max. 0.30 v 3.3 v (v ddsyn ) por asserted (ramp up) min. 0.0 max. 0.30 v ? spec 3: added new footnote 3 for both lines: ?it is possibl e to reach the current limit during ramp up--do not treat this event as a short circuit current.? ? spec 5: changed old footnote 1 (now foot note 2): ?user must be able to supply full operating current for the 1.5v supply when the 3.3v supply reaches this range.? to ?su pply full operating current for the 1.5 v supply when the 3.3 v supply reaches this range.? ? spec 10: ? changed the minimum values of: -40 c = 60; 25 c = 65; 150 c = 85. ? added old footnote 5 as new footnote 6. ? removed ?tj ?after ?150 c? in the last line, second column: characteristic. ? added a new footnote 7, ?refer to ta bl e 1 for the maximum operating frequency.? ? rewrote old footnote 7(new footnote 9) to: represents the worst-case external transistor beta. it is measured on a per part basis and calculated as (i dd i vrcctl ). ? added cross-reference to footnote 6: ?i vrcctl is measured at the following conditions: v dd = 1.35 v, v rc33 = 3.1 v, v vrcctl = 2.2 v.? changed ?(@ v dd = 1.35 v, f sys = f max )? to ?(@ f sys = f max ).? ? added new footnote 1 to spec 3: ? v il_s ( ta bl e 9 , spec 15) is guaranteed to scale with v ddeh6 down to v por5 . ? rewrote old footnote 7(new footnote 9) to: represents the worst-case external transistor beta. it is measured on a per part basis and calculated as (i dd i vrcctl ). ? deleted old footnote 8: ?preliminary value. final specification pending characterization.? table 28. table and figure changes between rev. 0.0 and 1.0 (continued) location description of changes
mpc5561 microcontroller data sheet, rev. 2.0 revision history for the mpc5561 data sheet freescale semiconductor 50 ta bl e 7 power sequence pin status for fast pads ? changed title to pin status for fast pads during the power sequence ? changed preceding paragraph from: although there are no power up/down sequencing requir ements to prevent issues like latch-up, excessive current spikes, etc., the state of the i/o pins during po wer up/down varies depending on power. prior to exiting por, the pads are in a hi gh impedance state (hi-z). to: there are no power up/down sequenc ing requirements to prevent issues such as latch-up, excessive current spikes, and so on. therefore, the state of the i/o pins during power up/down varies depending on which supplies are powered. ? deleted the ?comment? column. ? added a por column after the v dd column. ? added row 2:? v dde , low, low, asserted, high? and row 5: v dde , v dd33 , v dd , asserted, hi-z. ta bl e 8 power sequence pin status for medium/slow pads: ? changed title to pin status for medium and slow pads during the power sequence ? updated preceding paragraph. ? deleted the ?comment? column. ? added a por column after the v dd column. ? added row 3:? v ddeh , v dd , asserted, hi-z.? ta bl e 9 dc electrical specifications : ? spelled out meaning of the slash ?/? as ?and? as well as ?i/o? as ?input/output.? s entence still very confusing. deleted ?input/output? from t he specs to improve clarity. ? spec 20, column 2, characteristics ,? slow and medium output high voltage (i oh_s = ?2.0 ma):? created a left-justified second line and moved ?i oh_s = ?2.0 ma? from the 1st line to the second line and deleted the parentheses. created a left-justified third line that reads ?i oh_s = ?1.0 ma.? ? spec 20, column 4, min. : added a blank line before and after ?0.80 v ddeh ? and put ?0.85 v ddeh ? on the last line. ? spec 22, column 2,? slow and medium output low voltage (i ol_s = 2.0 ma) :? created a left-justified second line and moved ?i ol_s = 2.0 ma.? from the 1st line to the second line and deleted the parentheses. created a left-justified third line that reads ?i ol_s = 1.0 ma.? ? spec 22, column 5, max. : added a blank line before and after ?0.20 v ddeh ? and put ?0.15 v ddeh ? on the last line. ? spec 26: changed ?an[12]_ma[1]_sdo? to ?an[13]_ma[1]_sdo?. ? spec 27a: changed 132 mhz to 135 mhz. added maximum values for 8-way cache: 1.65 typical = 630 1.35 typical = 500 1.65 high = 785 1.35 high = 630 all 8-way cache max values have footnote 11. added 4-way cache with footnote 10: 1.65 high = 685 with footnote 11 1.35 high = tbd with footnote 12 ? spec 27b, operating current 1.5 v supplies @ 114 mhz: added maximum values for 8-way cache: 1.65 typical = 600, 1.35 typical = 450, 1.65 high = 680, 1.35 high = 500. all 8-way cache max values have footnote 11. added 4-way cache with footnote 10: 1.65 and 1.35 high = tbd with footnote 12 table 28. table and figure changes between rev. 0.0 and 1.0 (continued) location description of changes
revision history for the mpc5561 data sheet mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 51 ta bl e 9 dc electrical specifications : (continued) ? spec 27c, operating current 1.5 v supplies @ 82 mhz: added maximum values for 8-way cache: 1.65 typical = 490, 1.35 typical = 360, 1.65 high = 520, 1.35 high = 390. all 8-way cache max values have footnote 11. added 4-way cache values 1.65 high = tbd and 1.35 high = tbd, both with footnote 12. ? spec 28: changed 132 mhz to 135 mhz. ? spec 29: deleted frequency information. ? corrected footnote 3 to read: if standby operation is not requi red, connect the v stby to ground. ? combined old footnotes 11 and 12 for new footnote 6 and added to specs 27a, b, and c on the 8-way cache line that reads: eight-way cache enabled (l1csr0[corg] = 0b0). ? added footnote 10 to specs 27a, b, and c on the 4- way cache line that reads: four-way cache enabled (l1csr0[corg] = 0b1) or (l1csr0[corg] = 0b0 with l1csr0[wam] = 0b1, l1csr0[wid] = 0b1111, l1csr0[wdd] = 0b1111, l1csr0[awid] = 0b1, and l1csr0[awdd] = 0b1). ? added footnote 11 to specs 27a, b, and c on the max nu meric values: ?preliminary. specification pending final characterization.? ? added footnote 12 to specs 27a, b, and c on the max tb d values: ?specification pending final characterization.? figure 3 added figure to show interpolated idd stby values listed in ta bl e 9 . ta bl e 1 2 fmpll electrical characteristics : ? added (t a = t l ? t h ) to the second line of the table title. ? spec 1, footnote 1 in column 2: ?pll reference frequency range .?: changed to read ?nominal crystal and external reference values are worst-case not more than 1%. the device operates correctly if the frequency remains within 5% of the specification limit. this tolerance range allows for a slight frequency drift of the crystals over time. the designer must thoroughly understand the drift margin of the source clock.? ? spec 1, added two more lines to the pll reference frequency range ? to read as follows : crystal reference (20) fref_crystal 8 20 crystal reference (40) fref_crystal > 20 40 external reference (20) fref_ext 8 20 external reference (40) fref_ext > 20 40 ? spec 1, footnote 2 in column 2: ?pll reference frequency range .?: changed to: ?the 8?20 mhz crystal or external reference values have pllcfg[2] pulled low? and applies to spec 1, column 2, crystal reference and external reference. ? spec 1, footnote 2 in column 2: ?pll reference frequency range,? changed to: the 20?40 mhz crystal and external reference values have pllcfg[2] pulled hi gh, and the minimum frequen cy must be greater than 20 mhz. use the 8?20 mhz setting (pllcfg[2] pulled low) if a 20 mhz crystal or external reference is required. to exit reset when using 40 mhz, set pllcfg[2] to 1. ? specs 12 and 13: grouped (2 x cl). ? spec 21, column 2: changed f ref_crystal to f ref in ico frequency equation, and added the same equation but substituted f ref_ext for f ref for the external reference clock, giving: f ico = [ f ref_crystal (mfd + 4) ] (prediv + 1) f ico = [ f ref_ext (mfd + 4) ] (prediv + 1) ? spec 21, column 4, max.: deleted old footnote 18 that reads: the ico frequency can be higher than the maximum allo wable system frequency. for this case, set the cmpll synthesizer control register reduced frequency divider (fmpll_syncr[rfd]) to divide-by-two (rfd = 0b001). therefore, for a 40 mhz maximum device (system frequen cy), program the fmpll to generate 80 mhz at the ico output and then divide-by-two the rf d to provide the 40 mhz system clock.? ? spec 21: changed column 5 from ?82 or 66 mhz? to: ?150?. ? spec 22: changed column 4, max. value from f max to 20, and added footnote 20 to read, ?maximum value for dual controller (1:1) mode is (f max 2) and the predivider set to 1 (fmpll_syncr[prediv] = 0b001).? table 28. table and figure changes between rev. 0.0 and 1.0 (continued) location description of changes
mpc5561 microcontroller data sheet, rev. 2.0 revision history for the mpc5561 data sheet freescale semiconductor 52 ta bl e 1 3 eqadc conversion specifications : added (t a = t l ? t h ) to the table title. ta bl e 1 4 flash program and erase specifications: ? added (t a = t l ? t h ) to the table title. ? specs 7, 8, 9, and 10: changed typical values ? 48 kb: from 340 to 345; 64 kb: from 400 to 415 spec 8, 128kb block pre-program and erase time, max. column value from 15,000 to 7,500. ? moved footnote 1 from the table title to directly after the ?typical? in the column 5 header. ? footnote 2: changed from: ?initial factory condition: 100 program/erase cycles, 25 o c, typical supply voltage, 80 mhz minimum system frequency.? to: ?initial factory condition: 100 program/erase cycles, 25 o c, using a typical supply voltage measured at a minimum system frequency of 80 mhz.? ta bl e 1 5 flash eeprom module life : ? replaced (full temperature range) with (t a = t l ? t h ) in the table title. ? spec 1b, min. column value changed from 10,000 to 1,000. ta bl e 1 6 flash biu settings vs. frequency of operations : ? changed the maximum operating frequency column entry from: up to and including132 mhz to: up to and including134 mhz. ? added footnote 1 to the end of the table title, the footnot e reads: ?illegal combinations exist. use entries from the same row in this table.? ? moved footnote 2:? for maximum flash performance, set to 0b11? to the ?dpfen? column header. ? deleted the x-refs in the ?dpfen? column for the rows. ? created a x-ref for footnote 2 and inserted in the ?ipfen? column header. ? deleted the x-refs in the ?ipfen? column for the rows. ? moved footnote 3:? for maximum flash performance, set to 0b110? to the ?pflim? column header. ? deleted the x-refs in the ?pflim? column for the rows. ? moved footnote 4:? for maximum flash performance, set to 0b1? to the ?bfen? column header. ? deleted the x-refs in the ?bfen? column for the rows. ? changed footnote 6 from: ?a llows for 128 mhz system clock with 2% fr equency modulation? to: ?allows for 132 mhz system clock with 2% frequency modulation.? ta bl e 1 7 pad ac specifications and ta bl e 1 8 derated pad ac specifications : ? footnote 1, deleted ?f sys = 132 mhz.? ? footnote 2, changed from ?tested? to ?(not tested).? ? footnote 3, changed from ?out delay. . .? to ?the output delay. . .?, ? changed from ?add a maximum of one system clock to the output delay to get the output delay with respect to the system clock? to ?to calculate the output delay wi th respect to the system clock, add a maximum of one system clock to the output delay.? ? footnote 4: changed ?delay? to ?the output delay.? ? footnote 5: deleted ?before qualification.? ? changed from ?this parameter is suppl ied for reference and is not guaranteed by design and not tested? to ?this parameter is supplied for reference and is guaranteed by design and tested.? ta bl e 1 9 reset and configuration pin timing : footnote 1, deleted ?f sys = 132 mhz.? ta bl e 2 0 jtag pin ac electrical characteristics : ? footnote 1, deleted: ?f sys = 132 mhz.? and ?, and cl = 30 pf with dsc = 0b10, src = 0b11? ? footnote 1, changed ?functional? to ?nexus.? ta bl e 2 1 nexus debug port timing . ? changed spec 12, tck low to tdo data valid: changed ?vdde = 3.0 to 3.6 volts? maximum value in column 4 from 9 to 10. now reads ?vdde = 3.0?3.6 v? with a max value of 10. ? footnote 5, changed from ?to mcko. the timi ng is . . .? to: ? to ?mcko and is . . .? table 28. table and figure changes between rev. 0.0 and 1.0 (continued) location description of changes
revision history for the mpc5561 data sheet mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 53 5.2 information changed between revisions 1.0 and 2.0 the following table lists the ch anges made throughout the document. ta bl e 2 2 bus operation timing : ? changed spec 1 for the minimum 67 mhz column from: 15.2 to 14.9. ? specs 5 and 6: corrected format to show the bus timing values for various frequencies with ebts bit = 0 and ebts bit = 1. ta bl e 2 3 external interrupt timing : ? footnote 1: deleted ?f sys = 132 mhz?, ?.v dd33 and v ddsyn = 3.0?3.6 v? and ? and cl = 200 pf with src = 0b11.? ? deleted second figure after table ?external interrupt setup timing.? ta bl e 2 4 etpu timing , figure 16 etpu timing and figure 17 etpu input/output timing: deleted ? no etpu in mpc5561. ta bl e 2 4 emios timing : ? deleted (mts) from the heading, table, and footnotes. ? footnote 1: deleted ?. . .f sys = 132 mhz. . .?, ?. . .v dd33 and v ddsyn = 3.0?3.6 v. . .? and ? . . .and cl = 200 pf with src = 0b11.? ? added footnote 2: ?this specificatio n does not include the rise and fall times. when calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fields (src) of the pad configuration registers (pcr).? figure 16 emios timing added figure. ta bl e 2 5 dspi timing : ? added to beginning of footnote 1 ?all dspi timing specifications use the fastest slew rate (src = 0b11) on pad type m or mh. dspi signals using pad types of s or sh have an additional delay based on the slew rate.? ? footnote 1: deleted ?v dd = 1.35?1.65 v? and ?v dd33 and v ddsyn = 3.0?3.6 v. ta bl e 2 6 eqadc ssi timing characteristics : ? deleted from table title ?(pads at 3.3 v or 5.0 v)? ? deleted 1st line in table ?cload = 25 pf on all outputs. pad drive strength set to maximum.? ? spec 1: fck frequency -- removed. ? combined footnotes 1 and 2, and moved the new footno te to spec 2. moved old footnote 3 to spec 2. ? footnote 1, deleted ?v dd = 1.35?1.65 v? and ?v dd33 and v ddsyn = 3.0?3.6v.? changed ?cl = 50 pf? to ?cl = 25 pf.? ? footnote 2: added ?cycle? after ?duty? to read: fck duty cycle is not 50% when . . . . figure 27 mpc5561 324 package : ? changed ball la bel t21 from v rcvss to pllcfg2. ? deleted the version number and date. table 29. information changed between rev. 1.0 and rev. 2.0 location description of changes section 1, ?overview ?: added new 11th paragraph about flexray. remove d discussion in the siu and dspi paragraphs about deserialization and serialization, and chaini ng. removed reference to siu_disr register. ta bl e 6 vcr/por electrical specifications : added to specs 1, 2 and 3 that reads: on power up, assert reset before v por15 , v por33 , and v por5 negate (internal por). reset must remain asserted until the power supplies are within the operating conditions as specified in ta bl e 9 dc electrical specifications . on power down, assert reset before any power supplies fall outside the operating conditions and until the internal por asserts. table 28. table and figure changes between rev. 0.0 and 1.0 (continued) location description of changes
mpc5561 microcontroller data sheet, rev. 2.0 revision history for the mpc5561 data sheet freescale semiconductor 54 ta bl e 9 dc electrical specifications ? added footnote that reads: v dde2 and v dde3 are limited to 2.25?3.6 v only if ebts = 0; v dde2 and v dde3 have a range of 1.6?3.6 v if ebts =1. ? spec 27a, operating current 1.5 v supplies @ 135 mhz: -- 8-way 1.65 v typical use: from 630 to 620 -- 8-way 1.35 v typical use: from 500 to 440 -- 8-way 1.65 v high use: from 785 to 670 -- 8-way 1.35 v high use: from 630 to 490 -- 4-way 1.65 v high use: from 710 to 620 -- 4-way 1.35 v high use: from 550 to 430 ? spec 27b, operating current 1.5 v supplies @ 114 mhz: -- 8-way 1.65 v typical use: from 600 to 590 -- 8-way 1.35 v typical use: from 450 to 395 -- 8-way 1.65 v high use: from 680 to 580 -- 8-way 1.35 v high use: from 500 to 390 -- 4-way 1.65 v high use: from 650 to 550 -- 4-way 1.35 v high use: from 490 to 385 ? spec 27c, operating current 1.5 v supplies @ 82 mhz: -- 8-way 1.65 v typical use: from 490 to 485 -- 8-way 1.35 v typical use: from 360 to 320 -- 8-way 1.65 v high use: from 545 to 470 -- 8-way 1.35 v high use: from 400 to 315 -- 4-way 1.65 v high use: from 530 to 460 -- 4-way 1.35 v high use: from 395 to 310 ? removed footnote 12 on all these changed values: preliminary. specification pending final characterization. ta bl e 1 7 pad ac specifications ? footnote 1, changed ?v ddeh = 4.5?5.5;? to ?v ddeh = 4.5?5.25;? ? footnote 1, deleted ?f sys = 132 mhz.? ? footnote 2, changed from ?t ested? to ?(not tested).? ? footnote 3, changed from ?out delay. . .? to ?the output delay. . .?, ? changed from ?add a maximum of one system clock to the output delay to get the output delay with respect to the system clock? to ?to calculate the output delay with re spect to the system clock, add a maximum of one system clock to the output delay.? ? footnote 4: changed ?delay? to ?the output delay.? ? footnote 5: deleted ?before qualification.? ? changed from ?this parameter is supplied for reference a nd is not guaranteed by design and not tested? to ?this parameter is supplied for reference and is guaranteed by design and tested.? ta b l e 2 2 bus operation timing : ? external bus frequency in the table heading: added footnote that reads: speed is the nominal maximum frequency. max. speed is the maximum speed allowed in cluding frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm, and 135 mhz parts allow for 132 mhz system clock + 2% fm. ? spec 1: changed the values in min. columns: 40 mhz from 25 to 24.4; 56 mhz from 17.9 to 17.5 ? specs 7 and 8: removed from external bus interface: bdip , oe , tsiz[0:1], and we /be [0:3]. ? added a footnote each for the data[0:31], tea , and we /be [0:3] signals in the table: due to pin limitations, the data[16:31], tea , and we /be [2:3] signals are not available on the 324 package. table 29. information changed between rev. 1.0 and rev. 2.0 (continued) location description of changes
revision history for the mpc5561 data sheet mpc5561 microcontroller data sheet, rev. 2.0 freescale semiconductor 55 ta bl e 2 4 emios timing : ? footnote 1, changed ?v ddeh = 4.5?5.5;? to ?v ddeh = 4.5?5.25;? ? deleted (mts) from the heading, table, and footnotes. ? footnote 1: deleted ?. . .f sys = 132 mhz. . .?, ?. . .v dd33 and v ddsyn = 3.0?3.6 v. . .? and ? . . .and cl = 200 pf with src = 0b11.? ? added footnote 2: ?this specification does not include the rise and fall times. when calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fields (src) of the pad configuration registers (pcr).? ta bl e 2 5 dspi timing : ? footnote 1, changed ?v ddeh = 4.5?5.5;? to ?v ddeh = 4.5?5.25;? ? table title: added footnote that reads: speed is t he nominal maximum frequency. max. speed is the maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm, and 135 mhz parts allow for 132 mhz system clock + 2% fm. ta bl e 2 6 eqadc ssi timing characteristics : ? footnote 1, changed ?v ddeh = 4.5?5.5;? to ?v ddeh = 4.5?5.25;? ? deleted from table title ?(pads at 3.3 v or 5.0 v)? ? deleted 1st line in table ?cload = 25 pf on all outputs. pad drive strength set to maximum.? ? spec 1: fck frequency -- removed. ? combined footnotes 1 and 2, and moved the new foot note to spec 2. moved old footnote 3 to spec 2. ? footnote 1, deleted ?v dd = 1.35?1.65 v? and ?v dd33 and v ddsyn = 3.0?3.6v.? changed ?cl = 50 pf? to ?cl = 25 pf.? ? footnote 2: added ? cycle? after ?duty? to read: fck duty cycle is not 50% when . . . . figure 27 mpc5561 324 pbga pinouts: ? changed ball labels on the 324 pbga to show only signals available on the device: ? c1 -> pscs3, c2 -> pcsc4, ? d1 -> pcsc1, d2 -> pcsc2, d3 -> irq 14 ? e1 -> irq 12, e2 -> irq 15, e3 -> irq 13, e4 -> irq 9 ? f1 -> irq 11, f2 -> irq 10, f3 -> pdi_data6, f4 -> pdi_data7 ? g1 -> irq 8, g2 -> pdi_data8, g3 -> pcsb4, g4 -> pcsb3 ? h1 -> pdi_data5, h2 -> pcsb5, h3 -> pdichsel2 ? j1 -> pcsb1, j2 -> pdi_data0, j3 -> frn_rx, j4 -> pdichsel1 ? k1 -> pdichsel0, k2 -> gp io121, k3 -> pdi_frame_valid, k4 -> frbtxen, k19 -> rxdd ? l1 -> frbtx, l2 -> pdisnclk, l3 -> gpio114, l4 -> pdilinevalid, l20 -> pcsc5, l21 -> pcsc2, l22 -> pcsc1 ? m2 -> irq7, m19 -> pcsb2, m20 -> txdc, m21 -> txdd ? n19 -> rxdc, n21 -> pcsb3 ? ab18 -> pcsc3, ab19 -> pcsc4 table 29. information changed between rev. 1.0 and rev. 2.0 (continued) location description of changes
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